Bit Timing Configuration¶
In most cases the recommended settings for a predefined set of common
bitrates will work just fine. In some cases it may however be necessary to specify
custom settings. The
can.BitTiming class can be used for this purpose to
specify them in a relatively interface agnostic manner.
It is also possible to specify the same settings for a CAN 2.0 bus using the config file:
[default] bitrate=1000000 f_clock=8000000 tseg1=5 tseg2=2 sjw=1 nof_samples=1
[default] brp=1 tseg1=5 tseg2=2 sjw=1 nof_samples=1
[default] btr0=0x00 btr1=0x14
- class can.BitTiming(bitrate=None, f_clock=None, brp=None, tseg1=None, tseg2=None, sjw=None, nof_samples=1, btr0=None, btr1=None)¶
Representation of a bit timing configuration.
The class can be constructed in various ways, depending on the information available or the capabilities of the interfaces that need to be supported.
The preferred way is using bitrate, CAN clock frequency, TSEG1, TSEG2, SJW:
can.BitTiming(bitrate=1000000, f_clock=8000000, tseg1=5, tseg2=1, sjw=1)
If the clock frequency is unknown it may be omitted but some interfaces may require it.
Alternatively the BRP can be given instead of bitrate and clock frequency but this will limit the number of supported interfaces.
It is also possible specify BTR registers directly, but will not work for all interfaces:
bitrate (int) – Bitrate in bits/s.
f_clock (int) – The CAN system clock frequency in Hz. Usually the oscillator frequency divided by 2.
brp (int) – Bit Rate Prescaler. Prefer to use bitrate and f_clock instead.
tseg1 (int) – Time segment 1, that is, the number of quanta from (but not including) the Sync Segment to the sampling point.
tseg2 (int) – Time segment 2, that is, the number of quanta from the sampling point to the end of the bit.
sjw (int) – The Synchronization Jump Width. Decides the maximum number of time quanta that the controller can resynchronize every bit.
nof_samples (int) – Either 1 or 3. Some CAN controllers can also sample each bit three times. In this case, the bit will be sampled three quanta in a row, with the last sample being taken in the edge between TSEG1 and TSEG2. Three samples should only be used for relatively slow baudrates.
btr0 (int) – The BTR0 register value used by many CAN controllers.
btr1 (int) – The BTR1 register value used by many CAN controllers.